Summary
Silicon is the key building block of transistors, the workhorse of modern electronics. Since the early 2000s, scaling down the transistors’ size according to Moore’s Law to increase clock speed, decrease energy requirements and enhance compactness has been progressively more challenging than it had been for the previous 40 years. Reducing silicon at the two-dimensional level is a technological vision to achieve the ultimate shrinking of high-performance electronic devices and gain enough mechanical flexibility to make it integrable in low-power flexible devices. We propose to attain this breakthrough result by stabilizing silicene, an atomically thin silicon layer with a nearly graphene-like structure, by physically protecting both of its faces. Our goal is the scalable production of durable silicene in the form of atomically thin membranes. Standardized production of silicene membranes will be then assessed for integration into high-performance or low-power and flexible transistors with unprecedented outperforming technical advantages (intrinsic channel miniaturization, high carrier mobility, high energy efficiency, large-scale uniformity, high flexibility, and transfer compatibility with secondary substrates) and substantial reduction of the energy consumption. These characteristics make silicene membranes a promising component of a sustainable electronics for massive diffused societal trends like the internet-of-things. The goal of this PoC project is to validate with industrial players the technological feasibility of a prototypal silicene-based transistor, at the same time defining the best IP protection and commercialization route.
Unfold all
/
Fold all
More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/101069262 |
| Start date: | 01-06-2022 |
| End date: | 30-11-2023 |
| Total budget - Public funding: | - 150 000,00 Euro |
Cordis data
Original description
Silicon is the key building block of transistors, the workhorse of modern electronics. Since the early 2000s, scaling down the transistors’ size according to Moore’s Law to increase clock speed, decrease energy requirements and enhance compactness has been progressively more challenging than it had been for the previous 40 years. Reducing silicon at the two-dimensional level is a technological vision to achieve the ultimate shrinking of high-performance electronic devices and gain enough mechanical flexibility to make it integrable in low-power flexible devices. We propose to attain this breakthrough result by stabilizing silicene, an atomically thin silicon layer with a nearly graphene-like structure, by physically protecting both of its faces. Our goal is the scalable production of durable silicene in the form of atomically thin membranes. Standardized production of silicene membranes will be then assessed for integration into high-performance or low-power and flexible transistors with unprecedented outperforming technical advantages (intrinsic channel miniaturization, high carrier mobility, high energy efficiency, large-scale uniformity, high flexibility, and transfer compatibility with secondary substrates) and substantial reduction of the energy consumption. These characteristics make silicene membranes a promising component of a sustainable electronics for massive diffused societal trends like the internet-of-things. The goal of this PoC project is to validate with industrial players the technological feasibility of a prototypal silicene-based transistor, at the same time defining the best IP protection and commercialization route.Status
SIGNEDCall topic
ERC-2022-POC1Update Date
09-02-2023
Images
No images available.
Geographical location(s)
Structured mapping
Search
