Summary
Microelectronics components are at the core of our modern economies. The corresponding global market is exponentially growing at an annual pace of 10-15% and should reach the trillion $ by 2030. The techno-economic framework that has been driving this industry is based on Boolean logic, von Neumann architectures (with separated computing and memory units) and CMOS transistors. It is pictured by the famous Moore’s law, describing the continuous shrinking of transistor size. For years, Dennard’s scaling law of the power consumption provided a path to shrinking such transistors, while keeping the power density constant. However, as technological nodes become today as small tens of atoms, we are hitting fundamental limits, leading to heating and preventing this downscaling,. Simultaneously, the power consumption of information and communication technologies (ICT) represents nearly 5% of the world’s energy consumption. To mitigate these civilizational issues, new devices and architectures for ICT must be invented. The consensus reached by the microelectronics community is that to reduce power consumption (i) memory and logic units must be brought together and (ii) the inherent nonvolatile properties of ferroic materials are a valuable asset to avoid the static power consumption. UPLIFT proposes to develop the POC of a non-volatile, spin-based, ultralow power (aJ) logic-in-memory component, coined FESO, which harnesses the ferroelectric control of spin-charge interconversion discovered within the ERC FRESCO. We will pattern devices down to the 100 nm scale and aim for 100 mV output voltages, 1 ns operation speed and endurance >10^9 cycles. UPLIFT will benefit from a well-defined path towards the commercial exploitation, including a decade-long collaboration between the PI and two researchers from Spintec in Grenoble, with whom the PI is launching a start-up company that will exploit the patent portfolio filed within FRESCO. This POC project will serve both as a support and a propeller for the start-up, to be created in Q1 2024.
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| Web resources: | https://cordis.europa.eu/project/id/101113273 |
| Start date: | 01-09-2023 |
| End date: | 28-02-2025 |
| Total budget - Public funding: | - 150 000,00 Euro |
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Original description
Microelectronics components are at the core of our modern economies. The corresponding global market is exponentially growing at an annual pace of 10-15% and should reach the trillion $ by 2030. The techno-economic framework that has been driving this industry is based on Boolean logic, von Neumann architectures (with separated computing and memory units) and CMOS transistors. It is pictured by the famous Moore’s law, describing the continuous shrinking of transistor size. For years, Dennard’s scaling law of the power consumption provided a path to shrinking such transistors, while keeping the power density constant. However, as technological nodes become today as small tens of atoms, we are hitting fundamental limits, leading to heating and preventing this downscaling,. Simultaneously, the power consumption of information and communication technologies (ICT) represents nearly 5% of the world’s energy consumption. To mitigate these civilizational issues, new devices and architectures for ICT must be invented. The consensus reached by the microelectronics community is that to reduce power consumption (i) memory and logic units must be brought together and (ii) the inherent nonvolatile properties of ferroic materials are a valuable asset to avoid the static power consumption. UPLIFT proposes to develop the POC of a non-volatile, spin-based, ultralow power (aJ) logic-in-memory component, coined FESO, which harnesses the ferroelectric control of spin-charge interconversion discovered within the ERC FRESCO. We will pattern devices down to the 100 nm scale and aim for 100 mV output voltages, 1 ns operation speed and endurance >10^9 cycles. UPLIFT will benefit from a well-defined path towards the commercial exploitation, including a decade-long collaboration between the PI and two researchers from Spintec in Grenoble, with whom the PI is launching a start-up company that will exploit the patent portfolio filed within FRESCO. This POC project will serve both as a support and a propeller for the start-up, to be created in Q1 2024.Status
SIGNEDCall topic
ERC-2022-POC2Update Date
31-07-2023
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