Summary
Our solution is an innovative suite of hardware-agnostic quantum algorithms, along with their hardware-aware implementations. Our solution will consist of a complete, multi-level set of techniques that reduce quantum circuits’ size and improve their fidelity when executed on real quantum hardware.
We will enable relevant business problems, too difficult for conventional computing, to be solved several years earlier.
The exemplary solution consists of:
1) Application layer with problem reduced (classically) to the form best suited for QC. [In case of routing this is parallel TSP reduced, for example to max 2-SAT]
2) Optimisation layer containing features guaranteeing optimal representation given problem size. This includes our decomposition techniques for multi-control quantum gates
3) Implementation layer guaranteeing optimal use of the hardware (this includes hardware aware implementation, taking into account the topology (qubit connectivity) and native gate set.
We will enable relevant business problems, too difficult for conventional computing, to be solved several years earlier.
The exemplary solution consists of:
1) Application layer with problem reduced (classically) to the form best suited for QC. [In case of routing this is parallel TSP reduced, for example to max 2-SAT]
2) Optimisation layer containing features guaranteeing optimal representation given problem size. This includes our decomposition techniques for multi-control quantum gates
3) Implementation layer guaranteeing optimal use of the hardware (this includes hardware aware implementation, taking into account the topology (qubit connectivity) and native gate set.
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/190183782 |
| Start date: | 01-07-2023 |
| End date: | 30-06-2025 |
| Total budget - Public funding: | 4 628 617,50 Euro - 2 499 999,00 Euro |
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Original description
Our solution is an innovative suite of hardware-agnostic quantum algorithms, along with their hardware-aware implementations. Our solution will consist of a complete, multi-level set of techniques that reduce quantum circuits’ size and improve their fidelity when executed on real quantum hardware.We will enable relevant business problems, too difficult for conventional computing, to be solved several years earlier.
The exemplary solution consists of:
1) Application layer with problem reduced (classically) to the form best suited for QC. [In case of routing this is parallel TSP reduced, for example to max 2-SAT]
2) Optimisation layer containing features guaranteeing optimal representation given problem size. This includes our decomposition techniques for multi-control quantum gates
3) Implementation layer guaranteeing optimal use of the hardware (this includes hardware aware implementation, taking into account the topology (qubit connectivity) and native gate set.
Status
SIGNEDCall topic
HORIZON-EIC-2023-ACCELERATOROPEN-01Update Date
12-03-2024
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