Summary
Side channel attacks use, alongside information such as plaintexts or ciphertexts, leakage about the (secret) key-dependent intermediate state(s), and deliver a `key ranking' as a result. Kocher's attacks [15] [16] showed that for many practical implementations, observing a few encryptions made complete key recovery possible in practice. The academic research into combating these attacks so far has largely focused on approaches and tools to equip specialised cryptographic engineers with access to a specialist lab and tools.
The research hypothesis of this CoG is that one can make meaningful statements about the leakage behaviour of arbitrary implementations on small devices by utilising a-priori derived (instruction level) leakage models. Our vision is to enable developers with limited domain-specific knowledge to perform side channel evaluations at design time without access to a fully equipped lab, by creating tools and methodologies that integrate a priori derived instruction-level leakage models into a standard compiler.
This vision is articulated in three overarching research objectives:
1. Designing novel profiling strategies (WP1) including novel leakage acquisition techniques to generate leakage models for a specific target device.
2. Developing fast and comprehensive methods to support rapid evaluations (WP2).
3. Integration (WP3) of semantics, syntax and tools capable of using profiling information into a standard compiler with the aim to evaluate and improve the side channel resilience of the target code.
Addressing these goals simultaneously is required to make substantial progress towards the overall vision of this project.
As a final result, we will make demonstrators available (WP4): using a off-the shelf components, we supply the necessary tools and compiler enhancements including samples of cryptographic implementations to conduct analyses and demonstrate improvements regarding side channel resilience.
The research hypothesis of this CoG is that one can make meaningful statements about the leakage behaviour of arbitrary implementations on small devices by utilising a-priori derived (instruction level) leakage models. Our vision is to enable developers with limited domain-specific knowledge to perform side channel evaluations at design time without access to a fully equipped lab, by creating tools and methodologies that integrate a priori derived instruction-level leakage models into a standard compiler.
This vision is articulated in three overarching research objectives:
1. Designing novel profiling strategies (WP1) including novel leakage acquisition techniques to generate leakage models for a specific target device.
2. Developing fast and comprehensive methods to support rapid evaluations (WP2).
3. Integration (WP3) of semantics, syntax and tools capable of using profiling information into a standard compiler with the aim to evaluate and improve the side channel resilience of the target code.
Addressing these goals simultaneously is required to make substantial progress towards the overall vision of this project.
As a final result, we will make demonstrators available (WP4): using a off-the shelf components, we supply the necessary tools and compiler enhancements including samples of cryptographic implementations to conduct analyses and demonstrate improvements regarding side channel resilience.
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/725042 |
| Start date: | 01-09-2017 |
| End date: | 29-02-2024 |
| Total budget - Public funding: | 1 946 995,00 Euro - 1 946 995,00 Euro |
Cordis data
Original description
Side channel attacks use, alongside information such as plaintexts or ciphertexts, leakage about the (secret) key-dependent intermediate state(s), and deliver a `key ranking' as a result. Kocher's attacks [15] [16] showed that for many practical implementations, observing a few encryptions made complete key recovery possible in practice. The academic research into combating these attacks so far has largely focused on approaches and tools to equip specialised cryptographic engineers with access to a specialist lab and tools.The research hypothesis of this CoG is that one can make meaningful statements about the leakage behaviour of arbitrary implementations on small devices by utilising a-priori derived (instruction level) leakage models. Our vision is to enable developers with limited domain-specific knowledge to perform side channel evaluations at design time without access to a fully equipped lab, by creating tools and methodologies that integrate a priori derived instruction-level leakage models into a standard compiler.
This vision is articulated in three overarching research objectives:
1. Designing novel profiling strategies (WP1) including novel leakage acquisition techniques to generate leakage models for a specific target device.
2. Developing fast and comprehensive methods to support rapid evaluations (WP2).
3. Integration (WP3) of semantics, syntax and tools capable of using profiling information into a standard compiler with the aim to evaluate and improve the side channel resilience of the target code.
Addressing these goals simultaneously is required to make substantial progress towards the overall vision of this project.
As a final result, we will make demonstrators available (WP4): using a off-the shelf components, we supply the necessary tools and compiler enhancements including samples of cryptographic implementations to conduct analyses and demonstrate improvements regarding side channel resilience.
Status
CLOSEDCall topic
ERC-2016-COGUpdate Date
27-04-2024
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