Summary
One of the most exciting proposed solutions to the approaching limit of down-scaling in microelectronics (so-called “end of Moore’s law”) consists of the use of negative capacitors, [NegCap]s.
When a NegCap is placed between the gate and the channel of a FET (field-effect transistor), the applied voltage on the gate is strongly amplified on the channel. Therefore, it is possible to reduce substantially the applied gate voltage, yet keeping the voltage on the gate sufficiently high for on/off switching of the FET.
To continue the scaling down of basic electronic components such as FET, reduction of the applied voltage is essential in order to avoid overheating due to the too high power dissipation in the ultra high-density circuits. On the other hand, due to fundamental laws of physics, a minimum voltage of 60mV/decade is necessary for operation of the FET with currently available technologies. A way to solve these conflicting needs is to reduce the gate voltage and in parallel use a NegCap that will amplify the voltage on the channel.
But how to get a negative capacitor? In 2008 Salahuddin and Datta proposed to make NegCap using a ferroelectric capacitor. However, so far, experimental attempts failed to show the stable negative capacitance necessary for the voltage amplification on the FET gate. The key problem is that the ferroelectric splits into domains, which cancels the stabilized negative capacitance effect.
In our ERC-AdG project (“MOBILE-W”), we conceived a concept, supported by theory and modelling, that allows the fabrication of negative capacitors in which splitting to domains is prohibited. Here we aim to demonstrate this experimentally providing proof of concept, and find suitable framework and partners to translate our concept into commercial products. We believe that this will solve one of the major road-blocks for further scaling down of microelectronic circuits.
When a NegCap is placed between the gate and the channel of a FET (field-effect transistor), the applied voltage on the gate is strongly amplified on the channel. Therefore, it is possible to reduce substantially the applied gate voltage, yet keeping the voltage on the gate sufficiently high for on/off switching of the FET.
To continue the scaling down of basic electronic components such as FET, reduction of the applied voltage is essential in order to avoid overheating due to the too high power dissipation in the ultra high-density circuits. On the other hand, due to fundamental laws of physics, a minimum voltage of 60mV/decade is necessary for operation of the FET with currently available technologies. A way to solve these conflicting needs is to reduce the gate voltage and in parallel use a NegCap that will amplify the voltage on the channel.
But how to get a negative capacitor? In 2008 Salahuddin and Datta proposed to make NegCap using a ferroelectric capacitor. However, so far, experimental attempts failed to show the stable negative capacitance necessary for the voltage amplification on the FET gate. The key problem is that the ferroelectric splits into domains, which cancels the stabilized negative capacitance effect.
In our ERC-AdG project (“MOBILE-W”), we conceived a concept, supported by theory and modelling, that allows the fabrication of negative capacitors in which splitting to domains is prohibited. Here we aim to demonstrate this experimentally providing proof of concept, and find suitable framework and partners to translate our concept into commercial products. We believe that this will solve one of the major road-blocks for further scaling down of microelectronic circuits.
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| Web resources: | https://cordis.europa.eu/project/id/789758 |
| Start date: | 01-05-2018 |
| End date: | 31-10-2019 |
| Total budget - Public funding: | 150 000,00 Euro - 150 000,00 Euro |
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Original description
One of the most exciting proposed solutions to the approaching limit of down-scaling in microelectronics (so-called “end of Moore’s law”) consists of the use of negative capacitors, [NegCap]s.When a NegCap is placed between the gate and the channel of a FET (field-effect transistor), the applied voltage on the gate is strongly amplified on the channel. Therefore, it is possible to reduce substantially the applied gate voltage, yet keeping the voltage on the gate sufficiently high for on/off switching of the FET.
To continue the scaling down of basic electronic components such as FET, reduction of the applied voltage is essential in order to avoid overheating due to the too high power dissipation in the ultra high-density circuits. On the other hand, due to fundamental laws of physics, a minimum voltage of 60mV/decade is necessary for operation of the FET with currently available technologies. A way to solve these conflicting needs is to reduce the gate voltage and in parallel use a NegCap that will amplify the voltage on the channel.
But how to get a negative capacitor? In 2008 Salahuddin and Datta proposed to make NegCap using a ferroelectric capacitor. However, so far, experimental attempts failed to show the stable negative capacitance necessary for the voltage amplification on the FET gate. The key problem is that the ferroelectric splits into domains, which cancels the stabilized negative capacitance effect.
In our ERC-AdG project (“MOBILE-W”), we conceived a concept, supported by theory and modelling, that allows the fabrication of negative capacitors in which splitting to domains is prohibited. Here we aim to demonstrate this experimentally providing proof of concept, and find suitable framework and partners to translate our concept into commercial products. We believe that this will solve one of the major road-blocks for further scaling down of microelectronic circuits.
Status
CLOSEDCall topic
ERC-2017-PoCUpdate Date
27-04-2024
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