Summary
'The GR-GATE project proposes a novel negative quantum capacitance field effect transistor (NQCFET) with steep subthreshold characteristics which enables operation at low power supply voltages (Vdd). The technology can be combined with state of the art Si device architectures such as FDSOI or more mature steep slope switches such as the tunneling field effect transistor (TFET) functioning as technology booster to improve low power /high performance operation characteristics of transistors. The later can have an impact on energy efficient nanoelectronics. NQCFET has competitive advantages against rival emerging steep slope switch technologies and complements rather than competes with mainstream Si devices, therefore showing a high potential for non-disruptive innovation and a prospect for fast and smooth entry to large volume production.
The GR-GATE project will produce prototype transistor arrays at TRL 4 to show that the NQCFET technology is scalable to larger area wafers with acceptable device yield having reduced gate lengths and lower gate dielectric thickness in compliance with scaling trends and technological requirements as adopted by the industry. This will demonstrate that the technology has a commercial value calling for IP protection through an international patent filing. In addition, technology valorisation is planned in order to assess the manufacturability and viability of the NQCFET technology and identify further advanced development steps that need to be taken in order to bring the technology to maturity (TRL 8-9). It is expected that large European technology development laboratories will have a crucial role in validating the technology but also promoting it to their industrial affiliates targeting a licence agreement with key chip manufacturers to enable volume production. '
The GR-GATE project will produce prototype transistor arrays at TRL 4 to show that the NQCFET technology is scalable to larger area wafers with acceptable device yield having reduced gate lengths and lower gate dielectric thickness in compliance with scaling trends and technological requirements as adopted by the industry. This will demonstrate that the technology has a commercial value calling for IP protection through an international patent filing. In addition, technology valorisation is planned in order to assess the manufacturability and viability of the NQCFET technology and identify further advanced development steps that need to be taken in order to bring the technology to maturity (TRL 8-9). It is expected that large European technology development laboratories will have a crucial role in validating the technology but also promoting it to their industrial affiliates targeting a licence agreement with key chip manufacturers to enable volume production. '
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/790272 |
| Start date: | 01-03-2018 |
| End date: | 31-08-2019 |
| Total budget - Public funding: | 150 000,00 Euro - 150 000,00 Euro |
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Original description
'The GR-GATE project proposes a novel negative quantum capacitance field effect transistor (NQCFET) with steep subthreshold characteristics which enables operation at low power supply voltages (Vdd). The technology can be combined with state of the art Si device architectures such as FDSOI or more mature steep slope switches such as the tunneling field effect transistor (TFET) functioning as technology booster to improve low power /high performance operation characteristics of transistors. The later can have an impact on energy efficient nanoelectronics. NQCFET has competitive advantages against rival emerging steep slope switch technologies and complements rather than competes with mainstream Si devices, therefore showing a high potential for non-disruptive innovation and a prospect for fast and smooth entry to large volume production.The GR-GATE project will produce prototype transistor arrays at TRL 4 to show that the NQCFET technology is scalable to larger area wafers with acceptable device yield having reduced gate lengths and lower gate dielectric thickness in compliance with scaling trends and technological requirements as adopted by the industry. This will demonstrate that the technology has a commercial value calling for IP protection through an international patent filing. In addition, technology valorisation is planned in order to assess the manufacturability and viability of the NQCFET technology and identify further advanced development steps that need to be taken in order to bring the technology to maturity (TRL 8-9). It is expected that large European technology development laboratories will have a crucial role in validating the technology but also promoting it to their industrial affiliates targeting a licence agreement with key chip manufacturers to enable volume production. '
Status
CLOSEDCall topic
ERC-2017-PoCUpdate Date
27-04-2024
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