Summary
Artificial intelligence is increasingly being brought to the source of data, thus establishing the Edge AI concept. Edge AI is gaining momentum across various industries and services by public authorities and enables new applications requiring high performance, ultra-low latency with high bandwidth, efficient power use, and intelligence beyond regular computing. Its strategic importance is emphasised through the EU Chips Act monetary investments in the EU semiconductor supply chain, highlighting the urgent need for a qualified workforce. The advancements in Edge AI applications face critical research and engineering challenges related to limited computing and energy resources of the edge devices, limitations of the existing AI algorithms and their insufficient fit. Also, the related rapid technological advancements, market dynamics, interdisciplinarity, and regulatory uncertainty set a unique challenge for the valorisation and management of Edge-AI innovations. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management.
The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - PUNCH, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.
The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - PUNCH, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.
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Web resources: | https://cordis.europa.eu/project/id/101169378 |
Start date: | 01-09-2024 |
End date: | 31-08-2028 |
Total budget - Public funding: | - 3 851 294,00 Euro |
Cordis data
Original description
Artificial intelligence is increasingly being brought to the source of data, thus establishing the Edge AI concept. Edge AI is gaining momentum across various industries and services by public authorities and enables new applications requiring high performance, ultra-low latency with high bandwidth, efficient power use, and intelligence beyond regular computing. Its strategic importance is emphasised through the EU Chips Act monetary investments in the EU semiconductor supply chain, highlighting the urgent need for a qualified workforce. The advancements in Edge AI applications face critical research and engineering challenges related to limited computing and energy resources of the edge devices, limitations of the existing AI algorithms and their insufficient fit. Also, the related rapid technological advancements, market dynamics, interdisciplinarity, and regulatory uncertainty set a unique challenge for the valorisation and management of Edge-AI innovations. The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management.The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. The consortium is strategically designed to foster cross-disciplinary synergies, by seamlessly integrating innovation management research with the technical aspects of Edge AI design. The non-academic sector is represented by a European flagship R&D hub for nanoelectronics - IMEC, a global leader in industrial electronics and the largest semiconductor manufacturer in Germany - Infineon, a trusted automotive solutions provider - PUNCH, the worldwide leader in EDA tools development - Cadence. The academic excellence is established by the top ICT and Technology Innovation engineering universities and Europe's largest application-oriented research organisation - Fraunhofer.
Status
SIGNEDCall topic
HORIZON-MSCA-2023-DN-01-01Update Date
24-12-2024
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