Summary
REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and
variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :
i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a
Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness
(variability), speed, reduced footprint and cost.
ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a
memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits,
blocks and architectures will be carefully analysed from the power-consumption point of view.
In addition variability tolerant design techniques underpinned by variability analysis and statistical
simulation technology will be considered.
iii) Demonstration of a system on chip application using the developed memory solution and
benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also
require the redesign of different applications, including memory cells, and therefore we also propose the evaluation
of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative
materials.
The fulfilment of the objectives above will also imply the development of:
i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will
allow us to improve the CMOS technology by boosting device performance.
ii) New behavioural models, incorporating variability effects, to reach a deep understanding of
nanoelectronics devices
iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.
iv) Extreme low power solutions
The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.
variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :
i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a
Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness
(variability), speed, reduced footprint and cost.
ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a
memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits,
blocks and architectures will be carefully analysed from the power-consumption point of view.
In addition variability tolerant design techniques underpinned by variability analysis and statistical
simulation technology will be considered.
iii) Demonstration of a system on chip application using the developed memory solution and
benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also
require the redesign of different applications, including memory cells, and therefore we also propose the evaluation
of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative
materials.
The fulfilment of the objectives above will also imply the development of:
i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will
allow us to improve the CMOS technology by boosting device performance.
ii) New behavioural models, incorporating variability effects, to reach a deep understanding of
nanoelectronics devices
iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.
iv) Extreme low power solutions
The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/687931 |
| Start date: | 01-01-2016 |
| End date: | 30-06-2019 |
| Total budget - Public funding: | 4 543 793,75 Euro - 3 597 418,00 Euro |
Cordis data
Original description
REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption andvariability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are :
i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a
Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness
(variability), speed, reduced footprint and cost.
ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a
memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits,
blocks and architectures will be carefully analysed from the power-consumption point of view.
In addition variability tolerant design techniques underpinned by variability analysis and statistical
simulation technology will be considered.
iii) Demonstration of a system on chip application using the developed memory solution and
benchmarking with alternative embedded memory blocks.
The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also
require the redesign of different applications, including memory cells, and therefore we also propose the evaluation
of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative
materials.
The fulfilment of the objectives above will also imply the development of:
i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will
allow us to improve the CMOS technology by boosting device performance.
ii) New behavioural models, incorporating variability effects, to reach a deep understanding of
nanoelectronics devices
iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices.
iv) Extreme low power solutions
The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.
Status
CLOSEDCall topic
ICT-25-2015Update Date
27-10-2022
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Organisations
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| UNIVERSIDAD DE GRANADA (UGR) (Coördinator)
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| CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
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| COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (CEA)
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| Gold Standard Simulations ltd (GSS)
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| IBM RESEARCH GMBH
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| INSTITUT POLYTECHNIQUE DE GRENOBLE
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| Korea Institute of Science and Technology
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| STMICROELECTRONICS SA (ST SA)
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| SURECORE LTD (SURECORE)
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| SYNOPSYS (NORTHERN EUROPE) LIMITED (SNPS)
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| UNIVERSITE GRENOBLE ALPES
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| UNIVERSITY OF GLASGOW