Summary
Space markets have entered a new age, thanks to new business models but also to the increased use of deeply integrated electronics aboard satellites, either for digital or analog functions. Such miniaturized equipment allows for drastic reductions of the satellite mass, thus enabling larger payloads and more service revenues, and/or lighter satellites, and then cheaper launches.
However, despite the deep submicron technologies currently used for manufacturing space components, efficient and competitive packaging of large components remains a roadblock in trying to downsize further these equipment. This is especially true when we have to address dies beyond 300 mm² and/or beyond 625 pins, such integration being made worse with ever increased power dissipation, up to 10 or 20 W per die.
Following-up innovative approaches already developed by the Consortium members, such as European rad-hard FPGA (e.g. BRAVE, DAHLIA, OR VEGAS/OPERA projects), System In Package (SIP) technologies and High Density PCB as experienced with ESA contracts, the principal objective of this project is to design and ECSS qualify a “macro-component” Demonstration Model (DM) for space applications, offering unmatched Figures of Merit for space packaging, in terms of Interconnexion density, Die surface, Integration density, together with a cost reduction factor of 3 compared to ceramic CGA, among others. These challenges are made reachable within a 3-phase program, leveraging advanced technologies in organic high density low CTE PCBs, innovative thermal management and SIP integration up to a TRL7 stage, validating the full industrial processes vs. the ECSS Q ST standards.
Furthermore, thanks to the close partnership we have in our Consortium, this COMAP-4S Project will set the stage for a true European supply chain serving additional markets beyond rad-hard space equipment, such as embedded macro-components for Defense or Aeronautics, being fully in line with the objectives of SPACE-10-TEC-2019.
However, despite the deep submicron technologies currently used for manufacturing space components, efficient and competitive packaging of large components remains a roadblock in trying to downsize further these equipment. This is especially true when we have to address dies beyond 300 mm² and/or beyond 625 pins, such integration being made worse with ever increased power dissipation, up to 10 or 20 W per die.
Following-up innovative approaches already developed by the Consortium members, such as European rad-hard FPGA (e.g. BRAVE, DAHLIA, OR VEGAS/OPERA projects), System In Package (SIP) technologies and High Density PCB as experienced with ESA contracts, the principal objective of this project is to design and ECSS qualify a “macro-component” Demonstration Model (DM) for space applications, offering unmatched Figures of Merit for space packaging, in terms of Interconnexion density, Die surface, Integration density, together with a cost reduction factor of 3 compared to ceramic CGA, among others. These challenges are made reachable within a 3-phase program, leveraging advanced technologies in organic high density low CTE PCBs, innovative thermal management and SIP integration up to a TRL7 stage, validating the full industrial processes vs. the ECSS Q ST standards.
Furthermore, thanks to the close partnership we have in our Consortium, this COMAP-4S Project will set the stage for a true European supply chain serving additional markets beyond rad-hard space equipment, such as embedded macro-components for Defense or Aeronautics, being fully in line with the objectives of SPACE-10-TEC-2019.
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More information & hyperlinks
| Web resources: | https://cordis.europa.eu/project/id/870356 |
| Start date: | 01-01-2020 |
| End date: | 30-06-2024 |
| Total budget - Public funding: | 3 000 275,00 Euro - 2 975 275,00 Euro |
Cordis data
Original description
Space markets have entered a new age, thanks to new business models but also to the increased use of deeply integrated electronics aboard satellites, either for digital or analog functions. Such miniaturized equipment allows for drastic reductions of the satellite mass, thus enabling larger payloads and more service revenues, and/or lighter satellites, and then cheaper launches.However, despite the deep submicron technologies currently used for manufacturing space components, efficient and competitive packaging of large components remains a roadblock in trying to downsize further these equipment. This is especially true when we have to address dies beyond 300 mm² and/or beyond 625 pins, such integration being made worse with ever increased power dissipation, up to 10 or 20 W per die.
Following-up innovative approaches already developed by the Consortium members, such as European rad-hard FPGA (e.g. BRAVE, DAHLIA, OR VEGAS/OPERA projects), System In Package (SIP) technologies and High Density PCB as experienced with ESA contracts, the principal objective of this project is to design and ECSS qualify a “macro-component” Demonstration Model (DM) for space applications, offering unmatched Figures of Merit for space packaging, in terms of Interconnexion density, Die surface, Integration density, together with a cost reduction factor of 3 compared to ceramic CGA, among others. These challenges are made reachable within a 3-phase program, leveraging advanced technologies in organic high density low CTE PCBs, innovative thermal management and SIP integration up to a TRL7 stage, validating the full industrial processes vs. the ECSS Q ST standards.
Furthermore, thanks to the close partnership we have in our Consortium, this COMAP-4S Project will set the stage for a true European supply chain serving additional markets beyond rad-hard space equipment, such as embedded macro-components for Defense or Aeronautics, being fully in line with the objectives of SPACE-10-TEC-2019.
Status
SIGNEDCall topic
SPACE-10-TEC-2018-2020Update Date
27-10-2022
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H2020-EU.2.1.6.1. Enabling European competitiveness, non-dependence and innovation of the European space sector
