Optimizing streaming stencil time-step designs via FPGA floorplanning

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Authors: Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele, Marco D. Santambrogio

Journal title: 2017 27th International Conference on Field Programmable Logic and Applications (FPL)

Journal publisher: IEEE

Published year: 2017

Published pages: 1-4

DOI identifier: 10.23919/FPL.2017.8056764

ISBN: 978-9-0903-0428-1