How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt

Journal title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Journal number: 37/3

Journal publisher: Institute of Electrical and Electronics Engineers

Published year: 2018

Published pages: 629-642

DOI identifier: 10.1109/TCAD.2017.2717786

ISSN: 0278-0070