Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis

Summary

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: Liang Ma, Luciano Lavagno, Mihai Teodor Lazarescu, Arslan Arif

Journal title: IEEE Access

Journal number: 5

Journal publisher: Institute of Electrical and Electronics Engineers Inc.

Published year: 2017

Published pages: 18953-18974

DOI identifier: 10.1109/ACCESS.2017.2750923

ISSN: 2169-3536