Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

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Authors: Mukherjee, C., Poittevin, A., O'Connor, I., Larrieu, G., Maneux, C.

Journal title: Solid-State Electronics

Journal publisher: Pergamon Press Ltd.

Published year: 2021

DOI identifier: 10.1016/j.sse.2021.108125

ISSN: 0038-1101