Performance and design considerations for gate-all-around stacked-NanoWires FETs

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: S. Barraud, V. Lapras, B. Previtali, M. P. Samson, J. Lacord, S. Martinie, M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J. C. Barbe, M. Vinet, T. Ernst

Journal title: 2017 IEEE International Electron Devices Meeting (IEDM)

Journal publisher: IEEE

Published year: 2017

Published pages: 29.2.1-29.2.4

DOI identifier: 10.1109/iedm.2017.8268473

ISBN: 978-1-5386-3559-9