Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

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Authors: S. Barraud, V. Lapras, M.P. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. M. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Posseme, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet

Journal title: 2016 IEEE International Electron Devices Meeting (IEDM)

Journal publisher: IEEE

Published year: 2016

Published pages: 17.6.1-17.6.4

DOI identifier: 10.1109/IEDM.2016.7838441

ISBN: 978-1-5090-3902-9