A novel SRAM — STT-MRAM hybrid cache implementation improving cache performance

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Authors: Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit

Journal title: 2017 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

Journal publisher: IEEE

Published year: 2017

Published pages: 39-44

DOI identifier: 10.1109/NANOARCH.2017.8053704

ISBN: 978-1-5090-6037-5