Clock Reduction in Timed Automata While Preserving Design Parameters

Summary

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: Beyazit Yalcinkaya, Ebru Aydin Gol

Journal title: 2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)

Journal publisher: IEEE

Published year: 2019

Published pages: 31-40

DOI identifier: 10.1109/formalise.2019.00010

ISBN: 978-1-7281-3373-7