The Validation of Graph Model-Based, Gate Level Low-Dimensional Feature Data for Machine Learning Applications

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Authors: Aneesh Balakrishnan, Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Maksim Jenihhin

Journal title: 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

Journal publisher: IEEE

Published year: 2019

Published pages: 1-7

DOI identifier: 10.1109/norchip.2019.8906974

ISBN: 978-1-7281-2769-9