Hierarchical temporal memory implementation on FPGA using LFSR based spatial pooler address space generator

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Authors: Madis Kerner, Kalle Tammemae

Journal title: 2017 IEEE 20th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

Journal publisher: IEEE

Published year: 2017

Published pages: 92-95

DOI identifier: 10.1109/ddecs.2017.7934577

ISBN: 978-1-5386-0472-4