A 16-bit floating-point near-sram architecture for low-power sparse matrix-vector multiplication

This is a publication. If there is no link to the publication on this page, you can try the pre-formated search via the search engines listed on this page.

Authors: Eggermann, G., Rios, M., Ansaloni, G., Nassif, S. and Atienza, D.

Journal title: In 2023 IFIP/IEEE 31st International Conference on Very Large-Scale Integration (VLSI-SoC) In 2023 IFIP/IEEE 31st International Conference on Very Large-Scale Integration (VLSI-SoC)

Journal publisher: IEEE

Published year: 2023

DOI identifier: 10.1109/vlsi-soc57769.2023.10321838

ISBN: 979-8-3503-2599-7