Validated 1st embodiment of magnetic controller

This is a device consisting of an array of 10×10 µm2 current lines or multiple array stackings obtained by traditional photolithography with intermediate planarization steps if needed, or other components but having equivalent end characteristics. The device also includes the functional circuitry arrangement and a control unit. The controller is responsible to drive each of the array lines up to 100mA. To this end, a programmable current source is designed and fabricated in CMOS technology providing enough current driving for each of the array lines (this depends on the FEA simulations and its resistance). The CAD software used to design (layout) masks generates a geometry file with information that needs to be converted by software into commands (a set of bits) that control the current flow in each of the array lines. A current flowing through each line can be switched ON and OFF as a memory address. The controller will also carry a serial digital interface that will allow those programming bits to be transferred from CAD software to the matrix device. The current intensity can also be programmed in order to evaluate the performance of the whole system and also compensate for temperature variations. It follows that the CMOS current driver needs to be integrated (connected) to the matrix of current lines (fabricated at INL) driving individual column and row lines. This embodiment is integrated as a System-in-Package hardware with CMOS driver dies and a silicon matrix of current lines assembled in a single substrate, properly packaged, interconnected and protected for operation during the poc. 2D and 3D packaging (stacking of dies) strategies are considered providing the proper alignment between the matrix of current lines and the substrate to be plated. For future scalability, a single CMOS die may be considered integrating the matrix of current lines and the addressable current sources necessary to drive the current lines.The demonstration includes the magnetic and electrical characterization of the device, including 2-dimensional mapping of generated micro-structured magnetic field under variable pattern configurations, such that the deviation of the experimentally determined maps is ≤ 10% with respect to the finite element analysis described in D2.1.