ERD

Patent and/or Journal paper-1

Project: NANOxCOMP

Updated at: 28-04-2024

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Performance optimization tool

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Updated at: 28-04-2024

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Logic synthesis and defect tolerance for memristive crossbar arrays

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Updated at: 28-04-2024

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Report and/or Article

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Updated at: 28-04-2024

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Spin-torque memristor based offset cancellation technique for sense amplifiers

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Noise-induced Performance Enhancement of Variability-aware Memristor Networks

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Updated at: 28-04-2024

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Integrated Synthesis Methodology for Crossbar Arrays

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Updated at: 28-04-2024

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Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

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Updated at: 28-04-2024

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Composition of switching lattices for regular and for decomposed functions

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Synthesis on switching lattices of Dimension-reducible Boolean functions

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Computing with Emerging Nanotechnologies

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

Project: NANOxCOMP

Updated at: 28-04-2024

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A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Analog Neural Network based on Memristor Crossbar Arrays

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Updated at: 28-04-2024

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Testability of Switching Lattices in the Stuck at Fault Model

Project: NANOxCOMP

Updated at: 28-04-2024

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Testability of Switching Lattices in the Cellular Fault Model

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

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Updated at: 28-04-2024

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Project acronym NANOxCOMP

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

Project: NANOxCOMP

Updated at: 28-04-2024

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Project acronym NANOxCOMP

Logic synthesis and testing techniques for switching nano-crossbar arrays

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Updated at: 28-04-2024

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Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Project: NANOxCOMP

Updated at: 28-04-2024

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Computing with nano-crossbar arrays: Logic synthesis and fault tolerance

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Resources

Selected filters:

Patent and/or Journal paper-1

Performance optimization tool

Logic synthesis and defect tolerance for memristive crossbar arrays

Report and/or Article

Spin-torque memristor based offset cancellation technique for sense amplifiers

Sensing schemes for STT-MRAMs structured with high TMR in low RA MTJs

Yield analysis of nano-crossbar arrays for uniform and clustered defect distributions

Noise-induced Performance Enhancement of Variability-aware Memristor Networks

Integrated Synthesis Methodology for Crossbar Arrays

Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling

Novel Methods for Efficient Realization of Logic Functions Using Switching Lattices

Composition of switching lattices for regular and for decomposed functions

Synthesis on switching lattices of Dimension-reducible Boolean functions

Optimal and heuristic algorithms to synthesize lattices of four-terminal switches

A Satisfiability-Based Approximate Algorithm for Logic Synthesis Using Switching Lattices

Computing with Emerging Nanotechnologies

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Defect-Tolerant Logic Synthesis for Memristor Crossbars with Performance Evaluation

A Fast Hill Climbing Algorithm for Defect and Variation Tolerant Logic Mapping of Nano-Crossbar Arrays

A Survey of Fault-Tolerance Algorithms for Reconfigurable Nano-Crossbar Arrays

Analog Neural Network based on Memristor Crossbar Arrays

Testability of Switching Lattices in the Stuck at Fault Model

Testability of Switching Lattices in the Cellular Fault Model

Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer

Logic Synthesis for Switching Lattices by Decomposition with P-Circuits

Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods

Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays

Logic synthesis and testing techniques for switching nano-crossbar arrays

Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis

Computing with nano-crossbar arrays: Logic synthesis and fault tolerance