Low power DRAM architecture specification and preliminary datasheet

This delieverable is linked to task T2.4. Already In run 1, a first preliminary implementation of a memory block optimized from the point of view of power comsuption will be included. Based on the characterization of this preliminary memory block, and the characterization of the specific memory cells fabricated in run 1, architectural considerations for the complete DRAM block implementation will be evaluated. In particular those that support low voltage and low power operation will be prioritized. Specific circuit topologies for decode, sense amplifier, refresh and timing control will be considered. This will culminate in a proposal for an optimal memory block architecture to fully exploit the FB-DRAM cell developed by the REMINDER project. A preliminary datasheet will be prepared in order to engage potential customers and ensure market considerations are catered for. The results and outcomes of these tasks will be collected in this deliverable.