CMOS Lot primary characterization

Electrical and structural characterization of the devices fabricated at the three programmed runs. This deliverable will content the results from Task T1.4. This task concerns the characterization of the processed memory devices. The statistical characterization carried out with industrial parametric probers (600 and 680 Keithley) aims to check the conformity of the full CMOS process with embedded 1T-DRAM. Thus the main technological parameters (dielectric thickness, sheet resistance, etc…) and electrical parameters (threshold voltage, current level in various regimes, etc…) are statistically measured on each wafer for all geometries (gate length, channel width, etc…) implemented on the test vehicle. Analyses of these electrical measurements allow controlling the various process steps and The first version of the deliverable will be submitted at M18 after the outcome of the first run. There will be upgraded versions after second run (M24) and after the third run M30. Three sets of memory structures will be fabricated in CMOS FD28 and FD14 technology: Run 1: Fabrication of optimized FB-DRAM solutions (selected after benchmarking of Run 0 devices) and first approach to the memory matrix. Run 2: Results from the first run will educate the memory array design of the second run, which will be limited to the optimized version of the best FB-DRAM variant. In addition, a second set of optimized FBDRAM solutions will be fabricated, taking into account the results of the first run. The devices and structures fabricated in WP1 will be carefully measured in WP2 and simulated in WP3, in order to extract the parameters of the compact models developed in WP4. Run 3: The data will be useful to define end-user applications using the optimized memory solution and to fabricate the memory demonstrator in Run 3.