Simulation of FB-DRAM variability using DOE and surface response techniques

This deliverable is linked to T3.4. It will contain the results of the analysis of the influence of the influence that the statistical variations of the technological parameters have on the performance of FB-DRAM cells (retention time, current levels, power consumption, etc.). The variability aspects of memory circuit-design and manufacturability with accurate leakage models will be taken into account. Methods which enable detailed predictions of variability at the circuit-level without sacrificing total simulation time will be developed. Activities will focus on two types of variability simulations: - Die-to-die variations. -Intra-die variations and component mismatch.