Fabrication of FB-DRAM memory cells using Si nanowires, and 3D integration.

This deliverable is linked to Task T1.5, which is the fabrication of memory cells targeting sub-14nm node. Especially this task will be focused on realistic architectures to address sub-14nm technological nodes: both FDSOI and TriGate architectures will be envisaged in the 14nm FDSOI route. Based on the evaluation of needed advanced process modules in T1.1 and definition of additional advanced process steps, A2RAM architectures will be processes based on a SiGe/Si heterostructure for both WRITE and READ operations. Ease of integration will be preserved in this prospective task aiming to take advantage of band structure engineering to improved major figures of merit at memory cell level. The following key points will be considered: - Architecture identification to address sub-14nm technological nodes with first TCAD evaluation of the benefit of 3D non-planar architecture compared to planar FDSOI (linked to WP3) and advantage of the positive impact of the heterostucture based advanced memory cell; - Advanced Lot processing following the 14FDSOI route and preserving the ease of integration; - First electrical characterization of processed advanced memory cells to address sub-14nm and feedback on TCAD results for TCAD optimization of the integrated architecture (linked WP2 & WP3).