Complete embedded

Linked with T4.5. Functional designs or memory arrays in order to find applicable solution for the read and write processes, to prove the integration of the RAM concept in a real products and to assess the performance of the memory cell in its environment. It consist of: -Addendum of an existing Process Design Kit (PDK) including the Design Rule Check (DRC) and Layout versus Schematic (LVS) codes compatible with the new devices. -Validation of PDK plus DRC/LVS and parasitic extraction rule decks needed to enable the design process. - Small scale standalone memory arrays conceived to demonstrate the feasibility of the memory integration and to enable silicon proofs of concept -Proof of concept of large-scale memory arrays for embedded applications.