Development of new characterization techniques for the extraction of “transient” parameters and memory performance

This deliverable is linked to Task T2.2. The goal of the task is to quantify the memory mechanisms is various devices already available at the technological partners of the Consortium. The deliverable will contain the results of the outputs achieved: -Probe the memory effect in various structures: (i) Scaled FD SOI MOSFETs, (ii) Double-gate FinFETs and nanowires. - Measurement of the impact of high temperature operation on the retention time, programming speed, and current margins on the different devices. - Provide inputs, which together with those of T2.3 and WP3, will guide the architecture design of devices to be fabricated in WP1 and models to be developed in WP4. - Validation of simulation results obtained in WP3. - Design of test pattern - Design of test algorithm (testability, system, procedures of failure analysis) - Electrical characteristic analysis (I-V, C-V) - Physical characteristic analysis (Atomic Probe Tomography, SIMS, EXAF, RBS, EELS, Stress/strain analysis)