Calibration of the 3DMSEMC simulator: FinFET, SiNW and FB-DRAM benchmarking.

Linked with T3.6. It will describe the activities developed and the results achieved during Implementation and validation of a 3DMS-EMC simulator for the study of next-generation nanowire transistors needed to overcome the problems arising from the aggressive scaling in the design and fabrication of ultimate device and, in particular, FB-DRAM cells. It also contain the benchmarking of future nanodevices using 3DMS-EMC (FinFET, SiNW and FBDRAM).