A Self-Aligned Gate-Last Process Applied to All-III–V CMOS on Si

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Authors: Adam Jonsson, Johannes Svensson, Lars-Erik Wernersson

Journal title: IEEE Electron Device Letters

Journal number: 39/7

Journal publisher: Institute of Electrical and Electronics Engineers

Published year: 2018

Published pages: 935-938

DOI identifier: 10.1109/led.2018.2837676

ISSN: 0741-3106