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CASK - Open-Source Custom Architectures for Sparse Kernels

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Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

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Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

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A Domain Specific Language for accelerated Multilevel Monte Carlo simulations

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A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification

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Customizable Memory Systems for High Performance Reconfigurable Architectures

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A Decoupled Access-Execute Architecture for Reconfigurable Accelerators

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Transparent In-Circuit Assertions for FPGAs

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A Scalable Dataflow Implementation of Curran’s Approximation Algorithm

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From exaflop to exaflow

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How effective are custom parallel memories

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The Case for Custom Parallel Memories: an Application-centric Analysis

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Periodic Reporting for period 2 - EXTRA (Exploiting eXascale Technology with Reconfigurable Architectures)

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Integration and final demonstrators

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F-CNN: An FPGA-based framework for training Convolutional Neural Networks

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A Domain Specific Approach to High Performance Heterogeneous Computing

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EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

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Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs

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NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

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Chapter Four - Data Flow Computing in Geoscience Applications

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EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

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EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing

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MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization

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An FPGA-based high-throughput stream join architecture

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Design and exploration of routing methods for NoC-based multicore systems

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Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach

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A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

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A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

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On How to Accelerate Iterative Stencil Loops

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On the Automation of High Level Synthesis of Convolutional Neural Networks

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Resources

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CASK - Open-Source Custom Architectures for Sparse Kernels

Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules

Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA

A Domain Specific Language for accelerated Multilevel Monte Carlo simulations

A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification

Customizable Memory Systems for High Performance Reconfigurable Architectures

A Decoupled Access-Execute Architecture for Reconfigurable Accelerators

Transparent In-Circuit Assertions for FPGAs

A Scalable Dataflow Implementation of Curran’s Approximation Algorithm

From exaflop to exaflow

How effective are custom parallel memories

The Case for Custom Parallel Memories: an Application-centric Analysis

Periodic Reporting for period 2 - EXTRA (Exploiting eXascale Technology with Reconfigurable Architectures)

Integration and final demonstrators

F-CNN: An FPGA-based framework for training Convolutional Neural Networks

A Domain Specific Approach to High Performance Heterogeneous Computing

EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits

Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs

NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors

Chapter Four - Data Flow Computing in Geoscience Applications

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing

MiCAP-Pro: a high speed custom reconfiguration controller for Dynamic Circuit Specialization

An FPGA-based high-throughput stream join architecture

Design and exploration of routing methods for NoC-based multicore systems

Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications

On How to Accelerate Iterative Stencil Loops

On the Automation of High Level Synthesis of Convolutional Neural Networks