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HLS Support for Polymorphic Parallel Memories

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Updated at: 27-04-2024

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An open reconfigurable research platform as stepping stone to exascale high-performance computing

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Updated at: 27-04-2024

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A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL

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From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equati...

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A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration

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Updated at: 27-04-2024

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Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

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Towards Application-Centric Parallel Memories

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Updated at: 27-04-2024

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In-Circuit FPGA Debugging using Parameterised Reconfigurations

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SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs

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Updated at: 27-04-2024

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Hardware Compilation of Deep Neural Networks: An Overview

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Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of H...

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FPGA-based PairHMM Forward Algorithm for DNA Variant Calling

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Updated at: 27-04-2024

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Optimizing streaming stencil time-step designs via FPGA floorplanning

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Quantum Chemistry in Dataflow: Density-Fitting MP2

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Updated at: 27-04-2024

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Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project

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Abacus turn model-based routing for NoC interconnects with switch or link failures

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Updated at: 27-04-2024

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ADAM - Automated Design Analysis and Merging for Speeding up FPGA Development

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Updated at: 27-04-2024

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The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems

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Updated at: 27-04-2024

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Superimposed in-circuit debugging for self-healing FPGA overlays

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CGRA Tool Flow for Fast Run-Time Reconfiguration

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Hierarchical force-based block spreading for analytical FPGA placement

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CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems,

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Project Handbook, e-mail reflector, web site and FTP site

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Initial demonstrators

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Resources

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HLS Support for Polymorphic Parallel Memories

An open reconfigurable research platform as stepping stone to exascale high-performance computing

A Parallel, Energy Efficient Hardware Architecture for the merAligner on FPGA Using Chisel HCL

From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equati...

A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfiguration

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Towards Application-Centric Parallel Memories

In-Circuit FPGA Debugging using Parameterised Reconfigurations

SICTA: A superimposed in-circuit fault tolerant architecture for SRAM-based FPGAs

Hardware Compilation of Deep Neural Networks: An Overview

Tool flow for automatic generation of architectures and test-cases to enable the evaluation of CGRAs in the context of H...

FPGA-based PairHMM Forward Algorithm for DNA Variant Calling

Optimizing streaming stencil time-step designs via FPGA floorplanning

Quantum Chemistry in Dataflow: Density-Fitting MP2

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project

Abacus turn model-based routing for NoC interconnects with switch or link failures

ADAM - Automated Design Analysis and Merging for Speeding up FPGA Development

The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems

Superimposed in-circuit debugging for self-healing FPGA overlays

CGRA Tool Flow for Fast Run-Time Reconfiguration

Hierarchical force-based block spreading for analytical FPGA placement

CRRS: Custom Regression and Regularisation Solver for Large-scale Linear Systems,

Project Handbook, e-mail reflector, web site and FTP site

Initial demonstrators