ERD

HEI and Error Handlers Implementation

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Voltage margins identification on commercial x86-64 multicore microprocessors

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

End-to-end UniServer TCO Analysis and Time-Dependent Performance Degradation

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

2nd Analysis of Processor Cores under Various Stress Conditions

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

2nd Analysis of On- Chip Caches and Dynamic Memories

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

1st Analysis of On-Chip Caches and Dynamic Memories

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Definition of the UniServer board

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Error-Resilient Hypervisor

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Frequency and time domain analysis of power delivery network for monolithic 3D ICs

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

MeRLiN - Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

DARE: Data-Access Aware Refresh via spatial-temporal application resilience on commodity servers

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Towards a property graph generator for benchmarking

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Access-aware DRAM failure-rate estimation under relaxed refresh operations

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Applic...

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

How to make SMT Tail Latency Friendly

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

On the Evaluation of the Total-Cost-of-Ownership Trade-offs in Edge vs Cloud deployments: A Wireless-Denial-of-Service C...

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

1st Vertical, Full System Integration, and Validation

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Resource Management Policies in the Hypervisor

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

1st Evaluation of the Prototype and Comparison to State-of-the- Art in terms of Energy, Security and Determined Metrics ...

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

1st Report on Metrics of Success Against State-of-the-Art

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

1st Report on Hypervisor / System Software Interface

Project: UniServer

Updated at: 29-04-2024

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Project acronym UniServer

Resources

Selected filters:

HEI and Error Handlers Implementation

Voltage margins identification on commercial x86-64 multicore microprocessors

End-to-end UniServer TCO Analysis and Time-Dependent Performance Degradation

2nd Analysis of Processor Cores under Various Stress Conditions

2nd Analysis of On- Chip Caches and Dynamic Memories

1st Analysis of On-Chip Caches and Dynamic Memories

Definition of the UniServer board

Error-Resilient Hypervisor

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs

Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor

DRAM Characterization under Relaxed Refresh Period Considering System Level Effects within a Commodity Server

Frequency and time domain analysis of power delivery network for monolithic 3D ICs

MeRLiN - Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment

RT Level vs. Microarchitecture-Level Reliability Assessment: Case Study on ARM(R) Cortex(R)-A9 CPU

DARE: Data-Access Aware Refresh via spatial-temporal application resilience on commodity servers

Towards a property graph generator for benchmarking

Access-aware DRAM failure-rate estimation under relaxed refresh operations

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Applic...

Harnessing Voltage Margins for Energy Efficiency in Multicore CPUs

A System-Level Voltage/Frequency Scaling Characterization Framework for Multicore CPUs

How to make SMT Tail Latency Friendly

On the Evaluation of the Total-Cost-of-Ownership Trade-offs in Edge vs Cloud deployments: A Wireless-Denial-of-Service C...

Variation-Aware Pipelined Cores through Path Shaping and Dynamic Cycle Adjustment: Case Study on a Floating-Point Unit

1st Vertical, Full System Integration, and Validation

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits

Minimization of Timing Failures in Pipelined Designs via Path Shaping and Operand Truncation

Resource Management Policies in the Hypervisor

1st Evaluation of the Prototype and Comparison to State-of-the- Art in terms of Energy, Security and Determined Metrics ...

1st Report on Metrics of Success Against State-of-the-Art

1st Report on Hypervisor / System Software Interface