ERD

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

An on-line testing technique for the scheduler memory of a GPGPU

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Updated at: 28-04-2024

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ESR2.1 IRP Effective techniques for secure and reliable systems validation

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Updated at: 28-04-2024

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ESR1.2 IRP Adaptive methods for fault tolerant embedded systems

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Updated at: 28-04-2024

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Reports on training events

Project: RESCUE

Updated at: 28-04-2024

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Report on recruitment process

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Updated at: 28-04-2024

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Comparing different approaches to the test of Reconfigurable Scan Networks

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

Single-Event Characterization of Xilinx UltraScale+ ® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

Towards Multidimensional Verification: Where Functional Meets Non-Functional

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Updated at: 28-04-2024

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About the functional test of the GPGPU scheduler

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Project: RESCUE

Updated at: 28-04-2024

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Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

On the functional test of the GPGPU scheduler

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

An extended GPGPU model to support detailed reliability analysis

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

On the evaluation of SEU effects in GPGPUs

Project: RESCUE

Updated at: 28-04-2024

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Project acronym RESCUE

Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA

Project: RESCUE

Updated at: 28-04-2024

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Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

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Updated at: 28-04-2024

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Optical Fault Injections: Most Often Used Setups

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Updated at: 28-04-2024

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Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

Project: RESCUE

Updated at: 28-04-2024

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A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

Project: RESCUE

Updated at: 28-04-2024

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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Project: RESCUE

Updated at: 28-04-2024

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DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Project: RESCUE

Updated at: 28-04-2024

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Optical Fault Injections: a Setup Comparison

Project: RESCUE

Updated at: 28-04-2024

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IN-FIELD GPGPU TEST WITH SBST TECHNIQUES

Project: RESCUE

Updated at: 28-04-2024

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Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

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Updated at: 28-04-2024

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An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects

Project: RESCUE

Updated at: 28-04-2024

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Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Project: RESCUE

Updated at: 28-04-2024

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Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach

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Updated at: 28-04-2024

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On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

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Updated at: 28-04-2024

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A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores

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Updated at: 28-04-2024

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Resources

Selected filters:

Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL

An on-line testing technique for the scheduler memory of a GPGPU

ESR2.1 IRP Effective techniques for secure and reliable systems validation

ESR1.2 IRP Adaptive methods for fault tolerant embedded systems

Reports on training events

Report on recruitment process

Comparing different approaches to the test of Reconfigurable Scan Networks

Single-Event Characterization of Xilinx UltraScale+ ® MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation

Towards Multidimensional Verification: Where Functional Meets Non-Functional

About the functional test of the GPGPU scheduler

A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks

Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems

On the functional test of the GPGPU scheduler

An extended GPGPU model to support detailed reliability analysis

On the evaluation of SEU effects in GPGPUs

Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA

Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262

Optical Fault Injections: Most Often Used Setups

Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs

A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs

Optical Fault Injections: a Setup Comparison

IN-FIELD GPGPU TEST WITH SBST TECHNIQUES

Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks

An open source embedded-GPGPU model for the accurate analysis and mitigation of SEU effects

Accelerating Transient Fault Injection Campaigns by using Dynamic HDL Slicing

Testing permanent faults in pipeline registers of GPGPUs: A multi-kernel approach

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques

A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores