ERD

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challe...

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

3D Sequential Integration: Application-driven technological achievements and guidelines

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Breakthroughs in 3D Sequential technology

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

(Invited) 3D Monolithic Integration

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

3DVLSI, Technology and Application

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Data management plan (DMP)

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI Devices

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI...

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Periodic Project report 1

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analys...

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Low temperature high voltage analog devices in a 3D sequential integration

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Novel on-resistance based methodology for MOSFET electrical characterization

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Specification for the analog MOSFET

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Project Web-Page

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Low-temperature high-voltage analog MOSFET characterization

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

ST 28nm bottom tier processing finished

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Periodic Project report 2

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Final Report

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Test report physical implementation SinC modules

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Test and test report from TDC in 3D SinC

Project: 3D-MUSE

Updated at: 29-04-2024

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Project acronym 3D-MUSE

Periodic Reporting for period 3 - 3D-MUSE (3D Multi-Process Sequential Integration for Smart Sensor Interfaces)

Project: 3D-MUSE

Updated at: 18-07-2023

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Project acronym 3D-MUSE

Resources

Selected filters:

Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challe...

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors

A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit

3D Sequential Integration: Application-driven technological achievements and guidelines

Breakthroughs in 3D Sequential technology

(Invited) 3D Monolithic Integration

3DVLSI, Technology and Application

Data management plan (DMP)

Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI Devices

First Demonstration of Low Temperature (≤500°C) CMOS Devices Featuring Functional RO and SRAM Bitcells toward 3D VLSI...

Periodic Project report 1

28nm FDSOI CMOS Technology (FEOL and BEOL) Thermal Stability for 3D Sequential Integration: Yield and Reliability Analys...

Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations

Low temperature high voltage analog devices in a 3D sequential integration

Novel on-resistance based methodology for MOSFET electrical characterization

Specification for the analog MOSFET

Project Web-Page

Low-temperature high-voltage analog MOSFET characterization

ST 28nm bottom tier processing finished

Periodic Project report 2

Final Report

Test report physical implementation SinC modules

Test and test report from TDC in 3D SinC

Periodic Reporting for period 3 - 3D-MUSE (3D Multi-Process Sequential Integration for Smart Sensor Interfaces)